Synopsys Bengaluru Jobs for Freshers as R&D Engineer

Synopsys Bengaluru JobsSynopsys Schedule to hire R&D Engineer in Bengaluru for freshers. B.Tech / M.Tech in CS / EE Can Apply for this position. We are looking for R&D Engineer with Working knowledge of FPGA or static timing engine is a plus.

Company NameSynopsys
Company URL
Job RoleR&D Engineer
Job LocationBangalore / Bengaluru
QualificationB.Tech / M. Tech in CS / EE
Experience0 – 1 Years
Synopsys Bengaluru Jobs
Synopsys Bengaluru Jobs

Synopsys Bengaluru Jobs Description

Job Description:

Synopsys HAPS® Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Synopsys delivers ProtoCompiler and HAPS solution, which dramatically accelerate software development, hardware verification and system validation from individual IP blocks to processor subsystems to complete SoCs.

Looking for a R&D engineer in ProtoCompiler R&D team in Bangalore for the following role and with the given background/skill sets.

Roles and Responsibility:

  • A person in the position would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for partitioning, logic, timing optimization,  technology mapping steps of the FPGA prototyping software. 
  • The person is expected to
    • Given a requirement or functional specification, design and implement efficient data structures and algorithms in C/C++.
    • Work with AE team in test planning, execution and customer support.
    • Maintain and support existing product and features.

Synopsys Bengaluru Jobs skill:

The person is expected to have:

  • B.Tech/M. Tech in CS/EE from a reputed institute.
  • 0-2 years of experience in designing, developing and maintaining large EDA software. 
  • Sound knowledge in data structures, graph algorithms and C/C++ programming on Windows/Unix.
  • Familiarity in digital logic design.
  • Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis.
  • Working knowledge of FPGA or static timing engine is a plus

How to Apply: